[wplug] questions and clarification regarding RAM upper limits

[Bryan J. Smith]

Bill Moran <wmoran at potentialtech.com> wrote:
> On i386 arch, the maximum addressable memory is 4G,
> _unless_ you use PAE, which uses some tom-foolery to allow'
> i386 to address a full 2^64 of
> memory, albeit with some serious performance hits.  

Correct, it's 36-bit / 64GiB when Processor Address Extensions (PAE)
are enabled on any i686 "Pro" (non-consumer Intel) or any AMD
"Athlon" architecture.

SIDE NOTE:  AMD Athlon, even 32-bit, actually uses 40-bit EV6, and is
capable -- at the platform, register and even on-CPU AGPgart level --
of 40-bit / 1TiB addressing.

> The _theoretical_ limit for amd64 arch is 2^64, which I believe
> is 16T.

Actually, AMD x86-64 (Intel IA-32e) "Long Mode" is 48-bit / 256TiB,
using 52-bit / 4PiB registers, not 64-bit and there is no specified
64-bit mode at all (only a reservation).  This is a heavily
under-proliferated fact.  The 48-bit limitation is for maximum i486
TLB (and later) compatibility -- i.e., so 32-bit i486/686 binaries
can run on a "Long Mode" kernel.

To get around the limitations of "Long Mode," most everyone is likely
to use virtualization at the core (which is another discussion ;). 
No one has even laid out how such greater than 48-bit addressing
would work either.

> However, I don't think any CPUs/motherboards are actually able to
> do that at this time.
> AFAIK, the most you can get out of any CPU actually
> in production is 2^40.

As implemented, AMD64 and EM64T (the platform implementations of
x86-64 and IA-32e, respectively) are 40-bit / 1TiB.  This is a legacy
limitation of the Digital EV6 architecture, of which the x86-64
platform-level implementation is based on (long story).

Even though AMD uses HyperTransport, and Intel has its AGTL+ logic,
EV6 is still at the heart of the addressing and other logic. 
HyperTransport actually virtualizes most physical lines over is
"general" system interconnect, Intel is actually leverages its
previous AGTL+/PCI "peripheral" interconnect capabilities (many of
which are actually and still limited to 36-bit / 64GiB).

> The spec allows 2^64,

Actually, it does not (read the x86-64 Programming Manuals very
carefully ;).  There is no "specification" to support it yet, only a
"mode reservation."  There is really no "design" to address anything
beyond 48-bit / 256TiB, using the current 52-bit / 4PiB virtual
addressing /register modes.

> but the chip makers are saving some $$$ by not putting all
> those registers in, on the assumption that nobody out there
> will need a full 2^64 of memory for many years.

And any such mode would _break_ i486 TLB compatibility, so 32-bit
applications/libraries couldn't even run on such a kernel.  ;)

> Of course, if any of this information is wrong, I'll be happy to be
> corrected.

Actually, you're the first person I've met that got virtually
everything right.  Touche!


-- 
Bryan J. Smith   Professional, Technical Annoyance
b.j.smith at ieee.org    http://thebs413.blogspot.com
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