[wplug] redhat 8 SMP CPU detection

[Vanco, Donald]

Not being familiar with the platform - are the CPUs hyperthreading capable?
That would be my guess.  If so (and it's enabled) RHL will show 2 CPUs per
CPU installed.

Don

Lance Tost wrote:
> We got a new Dell PowerEdge 2650 in for a demo pre-installed with
> RedHat 
> 8.  It's a 2 CPU box but the funny thing is Linux is reporting 4 CPUs.
> Has anyone seen behavior like this?  You'd think being pre-installed,
> they would have made sure everything was working properly...
> 
> I actually did take the cover off to verify only two CPUs (BIOS also
> reports two CPUs). 
> 
> Here's some CPU info from dmesg:
> 
> CPU: L2 cache: 512K
> CPU: Physical Processor ID: 0
> CPU: After vendor init, caps: bfebfbff 00000000 00000000 00000000
> Intel machine check architecture supported.
> Intel machine check reporting enabled on CPU#0.
> CPU:     After generic, caps: bfebfbff 00000000 00000000 00000000
> CPU:             Common caps: bfebfbff 00000000 00000000 00000000
> Enabling fast FPU save and restore... done.
> Enabling unmasked SIMD FPU exception support... done.
> Checking 'hlt' instruction... OK.
> POSIX conformance testing by UNIFIX
> mtrr: v1.40 (20010327) Richard Gooch (rgooch at atnf.csiro.au)
> mtrr: detected mtrr type: Intel
> CPU: Before vendor init, caps: bfebfbff 00000000 00000000, vendor = 0
> CPU: L1 I cache: 0K, L1 D cache: 8K
> CPU: L2 cache: 512K
> CPU: Physical Processor ID: 0
> CPU: After vendor init, caps: bfebfbff 00000000 00000000 00000000
> Intel machine check reporting enabled on CPU#0.
> CPU:     After generic, caps: bfebfbff 00000000 00000000 00000000
> CPU:             Common caps: bfebfbff 00000000 00000000 00000000
> CPU0: Intel(R) Xeon(TM) CPU 2.80GHz stepping 07
> per-CPU timeslice cutoff: 1462.54 usecs.
> task migration cache decay timeout: 1 msecs.
> enabled ExtINT on CPU#0
> ESR value before enabling vector: 00000040
> ESR value after enabling vector: 00000000
> Booting processor 1/1 eip 2000
> Initializing CPU#1
> masked ExtINT on CPU#1
> ESR value before enabling vector: 00000000
> ESR value after enabling vector: 00000000
> Calibrating delay loop... 5573.87 BogoMIPS
> CPU: Before vendor init, caps: bfebfbff 00000000 00000000, vendor = 0
> CPU: L1 I cache: 0K, L1 D cache: 8K
> CPU: L2 cache: 512K
> CPU: Physical Processor ID: 0
> CPU: After vendor init, caps: bfebfbff 00000000 00000000 00000000
> Intel machine check reporting enabled on CPU#1.
> CPU:     After generic, caps: bfebfbff 00000000 00000000 00000000
> CPU:             Common caps: bfebfbff 00000000 00000000 00000000
> CPU1: Intel(R) Xeon(TM) CPU 2.80GHz stepping 07
> Booting processor 2/2 eip 2000
> Initializing CPU#2
> masked ExtINT on CPU#2
> ESR value before enabling vector: 00000000
> ESR value after enabling vector: 00000000
> Calibrating delay loop... 5573.87 BogoMIPS
> CPU: Before vendor init, caps: bfebfbff 00000000 00000000, vendor = 0
> CPU: L1 I cache: 0K, L1 D cache: 8K
> CPU: L2 cache: 512K
> CPU: Physical Processor ID: 3
> CPU: After vendor init, caps: bfebfbff 00000000 00000000 00000000
> Intel machine check reporting enabled on CPU#2.
> CPU:     After generic, caps: bfebfbff 00000000 00000000 00000000
> CPU:             Common caps: bfebfbff 00000000 00000000 00000000
> CPU2: Intel(R) Xeon(TM) CPU 2.80GHz stepping 07
> Booting processor 3/3 eip 2000
> Initializing CPU#3
> masked ExtINT on CPU#3
> ESR value before enabling vector: 00000000
> ESR value after enabling vector: 00000000
> Calibrating delay loop... 5573.87 BogoMIPS
> CPU: Before vendor init, caps: bfebfbff 00000000 00000000, vendor = 0
> CPU: L1 I cache: 0K, L1 D cache: 8K
> CPU: L2 cache: 512K
> CPU: Physical Processor ID: 3
> CPU: After vendor init, caps: bfebfbff 00000000 00000000 00000000
> Intel machine check reporting enabled on CPU#3.
> CPU:     After generic, caps: bfebfbff 00000000 00000000 00000000
> CPU:             Common caps: bfebfbff 00000000 00000000 00000000
> CPU3: Intel(R) Xeon(TM) CPU 2.80GHz stepping 07
> Total of 4 processors activated (22259.09 BogoMIPS).
> cpu_sibling_map[0] = 1 cpu_sibling_map[1] = 0
> cpu_sibling_map[2] = 3
> cpu_sibling_map[3] = 2